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CDC925DLRG4

CDC925DLRG4
Mfr. #:
CDC925DLRG4
Description:
Clock Synthesizer / Jitter Cleaner 133-MHz Clock Synth/ Drvr
Lifecycle:
New from this manufacturer.
Datasheet:
CDC925DLRG4 Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
CDC925DLRG4 more Information CDC925DLRG4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Clock Synthesizer / Jitter Cleaner
Maximum Input Frequency:
14.8 MHz
Supply Voltage - Max:
3.465 V
Supply Voltage - Min:
2.375 V
Minimum Operating Temperature:
0 C
Maximum Operating Temperature:
+ 85 C
Mounting Style:
SMD/SMT
Package / Case:
SSOP-56
Packaging:
Reel
Height:
2.59 mm
Length:
18.41 mm
Type:
PLL Clock Synthesizer
Width:
7.49 mm
Brand:
Texas Instruments
Operating Supply Voltage:
2.5 V, 3.3 V
Product Type:
Clock Synthesizers / Jitter Cleaners
Factory Pack Quantity:
1
Subcategory:
Clock & Timer ICs
Unit Weight:
0.024508 oz
Tags
CDC925D, CDC925, CDC92, CDC9, CDC
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC 133-MHZ CLOCK SYNTH 56-SSOP
***ark
IC, CLOCK SYNTHESIZER, 133MHZ, SSOP-56; Clock IC Type:Clock Synthesizer / Driver; Frequency:133MHz; No. of Outputs:19; Supply Current:12mA; Supply Voltage Range:3.135V to 3.465V, 2.375V to 2.625V; Digital IC Case Style:SSOP ;RoHS Compliant: Yes
***as Instruments
The CDC925 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100\. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN\ terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP\ or CPU_STOP\, the outputs operate normally. With a low-level applied to the PCI_STOP\ or CPU_STOP\ terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state. The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100\ control input. The PCI bus frequency is fixed to 33MHz. Since the CDC925 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.
Part # Description Stock Price
CDC925DLRG4
DISTI # CDC925DLRG4-ND		IC 133-MHZ CLOCK SYNTH 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)		Limited Supply - Call
    CDC925DLRG4
    DISTI # N/A    		Clock Synthesizer / Jitter Cleaner 133-MHz Clock Synth/ Drvr0
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      Availability
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      Available
      On Order:
      5500
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