SN65LVDS314RSKR

SN65LVDS314RSKR
Mfr. #:
SN65LVDS314RSKR
Description:
Serializers & Deserializers - Serdes Programmable 27b Serial-Parallel Rcvr
Lifecycle:
New from this manufacturer.
Datasheet:
SN65LVDS314RSKR Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
SN65LVDS314RSKR more Information SN65LVDS314RSKR Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Serializers & Deserializers - Serdes
RoHS:
Y
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Package / Case:
VQFN-64
Packaging:
Reel
Series:
SN65LVDS314
Brand:
Texas Instruments
Moisture Sensitive:
Yes
Product Type:
Serializers & Deserializers - Serdes
Factory Pack Quantity:
2000
Subcategory:
Interface ICs
Unit Weight:
0.008021 oz
Tags
SN65LVDS31, SN65LVDS3, SN65LVDS, SN65LVD, SN65LV, SN65L, SN65, SN6
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: info@omo-ic.com

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
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***AS INS
The SN65LVDS314 receiver de-serializes FlatLink™3G compliant serial input data to 27 parallel data outputs. The SN65LVDS314 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle.
***AS INSTRUM
The serial data and clock are received via Sub Low-Voltage Differential Signalling (SubLVDS) lines. The SN65LVDS314 supports three operating power modes (Shutdown, Standby, and Active) to conserve power.
***
When receiving, the PLL locks to the incoming clock CLK and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the Pixel clock PCLK generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK and DE held low, while all other parallel outputs are pulled high.
***
The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load designs.
***as Instr.
Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used to put the SN65LVDS314 in a Shutdown mode. The SN65LVDS314 enters an active Standby mode if the common mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., transmitter releases the CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS314 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with VDD = 0 V. This feature allows signal powerup before VDD is stabilized.
Part # Description Stock Price
SN65LVDS314RSKR
DISTI # C1S746203409797
LVDS Receiver 1755Mbps 64-Pin VQFN EP T/R
RoHS: Compliant
200
  • 100:$3.1100
  • 50:$3.8000
  • 10:$3.8400
  • 1:$5.2600
SN65LVDS314RSKR
DISTI # 296-34921-1-ND
IC RCVR SRL/PAR PROG 27BIT 64QFN
RoHS: Compliant
Min Qty: 1
Container: Cut Tape (CT)
3298In Stock
  • 1000:$2.4745
  • 500:$2.9340
  • 100:$3.4466
  • 10:$4.2070
  • 1:$4.6800
SN65LVDS314RSKR
DISTI # 296-34921-6-ND
IC RCVR SRL/PAR PROG 27BIT 64QFN
RoHS: Compliant
Min Qty: 1
Container: Digi-Reel®
3298In Stock
  • 1000:$2.4745
  • 500:$2.9340
  • 100:$3.4466
  • 10:$4.2070
  • 1:$4.6800
SN65LVDS314RSKR
DISTI # 296-34921-2-ND
IC RCVR SRL/PAR PROG 27BIT 64QFN
RoHS: Compliant
Min Qty: 2000
Container: Tape & Reel (TR)
Temporarily Out of Stock
  • 2000:$2.2823
SN65LVDS314RSKR
DISTI # SN65LVDS314RSKR
LVDS Receiver 64-Pin QFN T/R (Alt: SN65LVDS314RSKR)
RoHS: Compliant
Min Qty: 2000
Container: Tape and Reel
Europe - 0
  • 2000:€2.7900
  • 4000:€2.4900
  • 8000:€2.1900
  • 12000:€2.0900
  • 20000:€1.9900
SN65LVDS314RSKR
DISTI # SN65LVDS314RSKR
LVDS Receiver 64-Pin QFN T/R - Tape and Reel (Alt: SN65LVDS314RSKR)
RoHS: Compliant
Min Qty: 2000
Container: Reel
Americas - 0
  • 2000:$2.3900
  • 4000:$2.2900
  • 8000:$2.1900
  • 12000:$2.1900
  • 20000:$2.0900
SN65LVDS314RSKRProgrammable 27-Bit Serial-to-Parallel Receiver6000
  • 1000:$1.9500
  • 750:$2.0400
  • 500:$2.4200
  • 250:$2.8500
  • 100:$3.0400
  • 25:$3.4700
  • 10:$3.7200
  • 1:$4.1400
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Availability
Stock:
Available
On Order:
1984
Enter Quantity:
Current price of SN65LVDS314RSKR is for reference only, if you want to get best price, please submit a inquiry or direct email to our sales team sales@omo-ic.com
Reference price (USD)
Quantity
Unit Price
Ext. Price
1
$4.54
$4.54
10
$4.08
$40.80
100
$3.34
$334.00
250
$3.14
$785.00
500
$2.84
$1 420.00
1000
$2.40
$2 400.00
Due to semiconductor in short supply from 2021,below price is the Normal price before 2021.please send inquire to confirm.
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