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74ALVCH16600DLG4

74ALVCH16600DLG4
Mfr. #:
74ALVCH16600DLG4
Description:
Bus Transceivers 18-Bit Univ Bus Trncvr W/3-St Otpt
Lifecycle:
New from this manufacturer.
Datasheet:
74ALVCH16600DLG4 Datasheet
Delivery:
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ECAD Model:
More Information:
74ALVCH16600DLG4 more Information 74ALVCH16600DLG4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Bus Transceivers
RoHS:
Y
Logic Family:
74AL
Input Level:
LVTTL
Output Level:
LVTTL
Output Type:
3-State
High Level Output Current:
- 24 mA
Low Level Output Current:
24 mA
Propagation Delay Time:
6.8 ns
Supply Voltage - Max:
3.6 V
Supply Voltage - Min:
1.65 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Package / Case:
SSOP-56
Packaging:
Tube
Function:
Universal Bus Transceiver
Height:
2.59 mm
Length:
18.41 mm
Number of Circuits:
1
Product:
CMOS
Technology:
CMOS
Width:
7.49 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Number of Channels:
18
Supply Current - Max:
40 uA
Operating Supply Voltage:
1.65 V to 3.6 V
Polarity:
Non-Inverting
Product Type:
Bus Transceivers
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Triggering Type:
Negative Edge
Unit Weight:
0.024508 oz
Tags
74ALVCH16600D, 74ALVCH16600, 74ALVCH1660, 74ALVCH166, 74ALVCH1, 74ALVCH, 74ALVC, 74ALV, 74AL, 74A
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56
***i-Key
IC UNIV BUS TXRX 18BIT 56SSOP
***eco
18-BIT UBT W/CLK ENABLE
***el Nordic
Contact for details
***as Instruments
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16600 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, CLKBA\, and CLKENBA\. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Part # Description Stock Price
74ALVCH16600DLG4
DISTI # 74ALVCH16600DLG4-ND		IC UNIV BUS TXRX 18BIT 56SSOP
RoHS: Compliant
Min Qty: 120
Container: Tube		Limited Supply - Call
    74ALVCH16600DLG4
    DISTI # 595-74ALVCH16600DLG4    		Bus Transceivers 18-Bit Univ Bus Trncvr W/3-St Otpt
    RoHS: Compliant    		0
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      Availability
      Stock:
      Available
      On Order:
      5500
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      Current price of 74ALVCH16600DLG4 is for reference only, if you want to get best price, please submit a inquiry or direct email to our sales team sales@omo-ic.com
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